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Integrated Circuit Systems, Inc.
ICS9248-112
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: 810/810E type chipset. Output Features: * 2- CPUs @2.5V, up to 166.5MHz. * 9 - SDRAM @ 3.3V, up to150MHz including 1 free running * 8 - PCICLK @ 3.3V * 1 - IOAPIC @ 2.5V, PCI or PCI/2 MHz * 2 - 3V66MHz @ 3.3V, 2X PCI MHz * 1- 48MHz, @3.3V fixed. * 1- 24MHz, @3.3V fixed * 1- REF @3.3V, 14.318MHz. Features: * Up to 166MHz frequency support * Support FS0-FS3 strapping status bit for I2C read back. * Support power management: Through Power down Mode from I2C programming. * Spread spectrum for EMI control ( 0.25% center). * Spread can be enabled or disabled to all 32 frequencies throuth I2C. * Uses external 14.318MHz crystal Skew Specifications: * CPU - CPU: <175ps * SDRAM - SDRAM: < 250ps * 3V66 - 3V66: <175ps * PCI - PCI: <500ps * CPU-SDRAM<500ps * For group skew specifications, please refer to group timing relationship table.
Pin Configuration
VDDREF
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD. 1. These are double strength.
Block Diagram
Functionality
FS3 FS2 FS1 FS0 CPU (MHz) SDRAM (MHz) 3V66 (MHz) PCICLK (MHz) I OA P I C
1=PCICLK/2
I OA P I C
0=PCICLK
(MHz)
(MHz)
[1:0]
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
66.80 68.00 100.30 103.00 133.73 145.00 133.73 137.33 140.00 140.00 118.00 124.00 133.70 137.00 150.00 72.50
100.20 102.00 100.30 103.00 100.30 108.75 100.30 103.00 105.00 140.00 118.00 124.00 133.70 137.00 112.50 108.75
66.80 68.00 66.87 68.67 66.87 72.50 66.87 68.67 70.00 93.33 78.67 82.67 89.13 91.33 75.00 72.50
33.40 34.00 33.43 34.33 33.43 36.25 33.43 34.33 35.00 46.67 39.33 41.33 44.57 45.67 37.50 36.25
16.70 17.00 16.72 17.17 16.72 18.13 16.72 17.17 17.50 23.33 19.67 20.67 22.28 22.83 18.75 18.13
33.40 34.00 33.43 34.33 33.43 36.25 33.43 34.33 35.00 46.67 39.33 41.33 44.57 45.67 37.50 36.25
Additional frequencies programming.
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selectable
through
I2C
ICS9248-112
General Description
The ICS9248-112 is a single chip clock solution for designs using the 810/810E style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I 2 C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248112 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
GNDREF, VDDREF = REF0, X1, X2 GNDPCI , VDDPCI = PCICLK [9:0] GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F, supply for PLL core GND3V66 , VDD3V66 = 3V66 GND48 , VDD48 = 48MHz, 24_48MHz, VDDLAPIC = IOAPIC GNDLCPU , VDDLCPU = CPUCLK [1:0]
Pin Configuration
PIN NUMBER 1 2, 9, 10, 18, 25, 29, 37 3 4 5, 6, 14, 21, 28, 33, 41 7, 8 11 12 13, 15, 16, 17, 19, 20 22 23 24 26 27 PIN NAME REF1 VDD X1 X2 GND 3V66 (1:0) PCICLK01 FS0 PCICLK11 FS1 PCICLK (2:7) PD# SCLK SDATA 48MHz FS3 FS2 24MHz TYPE OUT PWR IN OUT PWR OUT OUT IN OUT IN OUT IN IN IN OUT IN IN OUT OUT OUT PWR OUT PWR OUT OUT IN DESCRIPTION 3.3V, 14.318MHz reference clock output. 3 . 3 V p ow e r s u p p l y Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF) Ground pins for 3.3V supply 3.3V clock outputs for HUB r unning at 2XPCI MHz 3.3V PCI clock outputs, with Synchronous CPUCLKS L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V PCI clock outputs, with Synchronous CPUCLKS L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V PCI clock outputs, with Synchronous CPUCLKS Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled and the VCO and the cr ystal are stopped. The latency of the p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s. Clock input of I2C input Data input for I2C serial input. 3.3V Fixed 48MHz clock output for USB L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V fixed 24MHz output 3.3V free r unning SDRAM not affected by I2C 3.3V outputs Ground for 2.5V power supply for CPU & APIC 2.5V Host bus clock output. 2.5V power supply for CPU, IOAPIC 2.5V clock output 3.3V, 14.318MHz reference clock output. If FREQ_APIC = 0, APIC Clock = PCICLK If FREQ_APIC = 1, APIC Clock = PCICLK/2 (default)
30 SDRAM_F 40, 39, 38, 36, SDRAM (7:0) 35, 34, 32, 31 42 43, 44 45, 47 46 48 GNDL CPUCLK (1:0) VDDL IOAPIC REF01 FREQ_IOAPIC
1
Double strength
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ICS9248-112
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9248-112
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit Bit (2, 7:4) CPUCLK (MHz) SDRAM (MHz) Description 3V66 (MHz) PCICLK (MHz) 33.40 34.00 33.43 34.33 33.43 36.25 33.43 34.33 35.00 46.67 39.33 41.33 44.57 45.67 37.50 36.25 37.50 13.83 36.67 40.00 41.67 34.63 35.00 38.33 48.33 33.25 50.00 33.25 51.67 55.50 38.33 33.25 FREQ_IOAPIC (MHz) 1 0 16.70 33.40 17.00 34.00 16.72 33.43 17.17 34.33 16.72 33.43 18.13 36.25 16.72 33.43 17.17 34.33 17.50 35.00 23.33 46.67 19.67 39.33 20.67 41.33 22.28 44.57 22.83 45.67 18.75 37.50 18.13 36.25 18.75 37.50 6.92 13.83 18.33 36.67 20.00 40.00 20.83 41.67 17.31 34.63 17.50 35.00 19.17 38.33 24.17 48.33 16.63 33.25 25.00 50.00 16.63 33.25 25.83 51.67 27.75 55.50 19.17 38.33 16.63 33.25 Spread Precentage +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center* +/- 0.25% Center* +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center +/- 0.25% Center* PWD
0 0 0 0 0 66.80 100.20 66.80 0 0 0 0 1 68.00 102.00 68.00 0 0 0 1 0 100.30 100.30 66.87 0 0 0 1 1 103.00 103.00 68.67 0 0 1 0 0 133.73 100.30 66.87 0 0 1 0 1 145.00 108.75 72.50 0 0 1 1 0 133.73 100.30 66.87 0 0 1 1 1 137.33 103.00 68.67 0 1 0 0 0 140.00 105.00 70.00 0 1 0 0 1 140.00 140.00 93.33 0 1 0 1 0 118.00 118.00 78.67 0 1 0 1 1 124.00 124.00 82.67 0 1 1 0 0 133.70 133.70 89.13 0 1 1 0 1 137.00 137.00 91.33 Bit 2, 0 1 1 1 0 150.00 112.50 75.00 Bit 7:4 0 1 1 1 1 72.50 108.75 72.50 1 0 0 0 0 75.00 112.50 75.00 1 0 0 0 1 83.00 83.00 27.67 1 0 0 1 0 110.00 110.00 73.33 1 0 0 1 1 120.00 120.00 80.00 1 0 1 0 0 125.00 125.00 83.33 1 0 1 0 1 69.25 103.88 69.25 1 0 1 1 0 70.00 105.00 70.00 1 0 1 1 1 76.67 115.00 76.67 1 1 0 0 0 145.00 145.00 96.67 1 1 0 0 1 66.50 99.75 66.50 1 1 0 1 0 150.00 150.00 100.00 1 1 0 1 1 99.75 99.75 66.50 1 1 1 0 0 155.00 155.00 103.33 1 1 1 0 1 166.50 166.50 111.00 1 1 1 1 0 153.33 115.00 76.67 1 1 1 1 1 133.00 99.75 66.50 0 - Frequency is selected by hardware select, Latched Inputs Bit 3 1 - Frequency is selected by Bit 2, 7:4 0 - Normal Bit 1 1 - Spread Spectrum Enabled 0.25% Center Spread 0 - Running Bit 0 1- Tristate all outputs
XXX Note1
0 1 0
Note 1: Default at power-up will be for latched logic inputs to define frequency(Bit 3 = 0). * These frequencies with spread enabled are equal to original Intel defined frequencies with -0.5% down spread.
I2C is a trademark of Philips Corporation
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ICS9248-112
Byte 1: Control Register (1= enable, 0 = disable)
Byte 2: SDRAM, Control Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 27 26 30
PWD X X X 1 1 1 1 1
DESCRIPTION FS3# FS0# FS2# 24MHz ( R e s e r ve d ) 48MHz ( R e s e r ve d ) SDRAM_F
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 31 32 34 35 36 38 39 40
PWD 1 1 1 1 1 1 1 1
DESCRIPTION SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Byte 3: PCI, Control Register (1= enable, 0 = disable)
Byte 4: Control Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 20 19 17 16 15 13 12 11
PWD 1 1 1 1 1 1 1 1
DESCRIPTION PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 8 7 46 43 44
PWD 0 1 1 X 1 X 1 1
DESCRIPTION ( R e s e r ve d ) 3V66_1 3V66_0 FREQ_IOAPIC# IOAPIC FS1# CPUCLK1 CPUCLK0
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Notes:
PIN# -
PWD 1 1 1 1 1 1 1 1
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 0
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Note: Don't write into this register. Writing into this register can cause malfunction
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ICS9248-112
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248112 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operation for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, then only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Fig. 1
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ICS9248-112
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 ms. The power down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9248-112
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Group Timing Relationship Table
CPU 66MHz CPU 100MHz CPU 133MHz Offset Tolerance Offset Tolerance Offset Tolerance CPU to SDRAM 2.5ns 500ps 5.0ns 500ps 0.0ns 500ps CPU to 3V66 7.5ns 500ps 5.0ns 500ps 0.0ns 500ps SDRAM to 3V66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps 3V66 to PCI 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps PCI to PCI 0.0ns 1.0ns 0.0ns 1.0ns 0.0ns 1.0ns USB & DOT Async N/A Async N/A Async N/A Group
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DD = 3.3 V +/-5%, V DDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Input High Voltage V IH 2 Input Low Voltage VIL VSS-0.3 VIN = VDD -5 Input High Current I IH VIN = 0 V; Inputs with no pull-up resistors -5 IIL1 Input Low Current VIN = 0 V; Inputs with pull-up resistors -200 IIL2 I DD3.3OP Operating Supply 300 CL = Max loads;Select @ 66 MHz Current I DD2.5OP 11 Power Down CL = Max loads; With input address to IDD3.3PD 300 Supply Current Vdd or Gnd Input Frequency Pin Inductance1 Input Capacitance1 Transition time Settling time1 Clk Stabilization1
1
MAX UNITS VDD+0.3 V 0.8 V 5 mA mA 350 15 600 mA mA MHz 5 6 45 3 3 3 nH pF pF pF ms ms ms
Fi Lpin CIN COUT CINX Ttrans Ts TSTAB
VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency From VDD = 3.3 V to 1% target frequency
14.312
27
1
Guaranteed by design, not 100% tested in production.
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ICS9248-112
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Impedance Output Impedance1 Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Skew window1 Jitter, Cycle-to-cycle1
1
1
SYMBOL RDSP2B RDSN2B V OH2B V OL2B I OH2B IOL2B t r2B t f2B dt2B tsk2B t jcyc-cyc2B
CONDITIONS VO = V DD*(0.5) VO = V DD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V V OL @ MAX = 0.3 V VOL = 0.4 V, V OH = 2.0 V VOH = 2.0 V, V OL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V; CPU=SDRAM=100,133 MHz CPU=67,133 MHz, SDRAM=100 MHz
MIN 13.5 12 2
-27 27 0.4 0.4 45
TYP 14 13 2.5 0.015 -85 -9 68 20 1.1 1.1 50 50 200 400
MAX UNITS 45 W 45 W V 0.4 V -27 mA mA ns ns % ps ps
30 1.6 1.6 55 175 250 500
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Impedance1 Output Impedance
1
SYMBOL RDSP1B RDSN1B V OH1 V OL1 I OH1 IOL1 t r1 t f1 dt1 t sk1 t jcyc-cyc1
CONDITIONS VO = V DD*(0.5) VO = V DD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 11 11 2.4
TYP 11 11 3.29 0.009 -136 -13 115 38 1.2 1.3 53.6 37 280
MAX UNITS 55 55 0.55 -33 W W V V mA mA ns ns % ps ps
Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
-33 30 0.5 0.5 45
40 2 2 55 175 500
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
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ICS9248-112
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1
1
SYMBOL RDSP4B1 RDSN4B1 VOH4B VOL4B I OH4B I OL4B tr4B tf4B dt4B
CONDITIONS VO = V DD*(0.5) VO = V DD*(0.5) I OH = -1 mA I OL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V VOL @ MAX = 0.3 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V, IOIAPIC=PCI/2 VT = 1.25 V VT = 1.25 V
MIN 9 9 2
TYP 14 16 2.5 0.011 -79 -10 66 20 0.9 0.9 50 130
MAX UNITS 30 30 0.4 -27 W W V V mA mA ns ns % ps
-27 27 0.4 0.4 45
30 1.6 1.6 55 500
Fall Time Duty Cycle1 Jitter, Cycle-to-cycle1 t jcyc-cyc4B
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER Output Impedance1 Output Impedance
1
SYMBOL RDSP3 RDSN3 VOH3 VOL3 IOH3 I OL3 t r3 t f3 dt3 t sk3 tjcyc-cyc
CONDITIONS V O = VDD*(0.5) V O = VDD*(0.5) I OH = -1 mA I OL = 1 mA V OH @ MIN = 2.0 V V OH @ MAX = 3.135 V V OL @ MIN = 1.0 V V OL @ MAX = 0.4 V V OL = 0.4 V, VOH = 2.4 V V OH = 2.4 V, VOL = 0.4 V V T = 1.5 V V T = 1.5 V V T = 1.5 V
MIN 9 9 2.4
TYP 9 9 3.3 0.01 -124 -20 105 46 1 1 53 98 170
MAX UNITS 24 24 0.4 -46 W W V V mA mA ns ns % ps ps
Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
-54 53 0.5 0.5 45
54 2 2 55 250 250
Duty Cycle Skew window1 Jitter1
1
Guaranteed by design, not 100% tested in production.
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ICS9248-112
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Impedance1 Output Impedance
1
SYMBOL RDSP1B RDSN1B V OH1 V OL1 I OH1 IOL1 t r1 t f1 dt1 t sk1 t jcyc-cyc1
CONDITIONS VO = V DD*(0.5) VO = V DD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 11 11 2.4
TYP 11 11 3.29 0.009 -136 -13 115 38 1.3 1.6 51.6 330 145
MAX UNITS 55 55 0.55 -33 W W V V mA mA ns ns % ps ps
Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
-33 30 0.5 0.5 45
40 2 2 55 500 500
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 26)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Impedance1 Output Impedance
1
SYMBOL RDSP5 RDSN5 V OH5 V OL5 I OH5 IOL5 t r5 t f5 dt5 t jcyc-cyc5
CONDITIONS VO = V DD*(0.5) VO = V DD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V; 48MHz VT = 1.5 V; REF
MIN 11 11 2.4
TYP 11 11 3.29 0.009 -136 -13 115 38 1.2 1.2 53 200 780
MAX UNITS 55 55 0.55 -23 W W V V mA mA ns ns % ps ps
Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Jitter, Cycle-to-cycle1
1
-29 29 0.5 0.5 45
40 4 4 55 500 1000
Guaranteed by design, not 100% tested in production.
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Pin 1
D/2
.093 DIA. PIN (Optional)
Index Area
E/2 PARTING LINE
H L DETAIL "A" TOP VIEW BOTTOM VIEW -eA2 c B A
.004 C
SEE DETAIL "A"
-E-DEND VIEW A1 SEATING PLANE -C-
SIDE VIEW
SYMBOL A A1 A2 B c D E e H h L N
COMMON DIMENSIONS MIN. NOM. MAX. .095 .102 .110 .008 .012 .016 .087 .090 .094 .008 .0135 .005 .010 See Variations .291 .295 .299 0.025 BSC .395 .420 .010 .013 .016 .020 .040 See Variations 0 8
VARIATIONS AC MIN. .620
D NOM. .625
N MAX. .630 48
"For current dimensional specifications, see JEDEC 95."
Dimensions in inches
48 Pin 300 mil SSOP Package
Ordering Information
ICS9248yF-112-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0326C--09/18/03
12

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